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? e92905b78-te sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. supports scsi phase commands. all scsi control signal are software controllable. all interrupt conditions are software maskable. built-in 4-bit general-use i/o port. programmable scsi rst drive time. programmable interrupt pin (irq) active logic level. single initiator mode detection logic. selection phase scsi parity check/ignore switch. pin compatible with cxd1185aq. (cxd1185cq only) comes in 64-pin qfp or 64-pin lqfp applications scsi controller structure cmos process absolute maximum ratings (ta=25 ?, v ss =0 v) supply voltage v dd v ss ?.5 to +7.0 v input voltage v i v ss ?.5 to v dd +0.5 v output voltage v o v ss ?.5 to v dd +0.5 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? description the cxd1185c is a high performance cmos scsi controller lsi that conforms to ansix3. 131- 1986 standards. the cxd1185c is capable of operating in both initiator and target modes. it satisfies all standard scsi bus features, such as arbitration, selection and parity generation/check functions. a 24-bit data transfer byte counter and 16-byte fifo are built into the hardware. two separate buses for data and processor makes high speed data transfer possible. 48 ma (sinking) port is built-in to achieve reduction in the number of external components. the chip offers a set of high level commands at scsi phase level. it is also possible to read/write all individual scsi signals. the combination of the above two makes programs simpler and at the same time improves programmability. features satisfies all scsi bus features, including arbitration, selection, parity generation/check and synchronous data transfer. maximum synchronous data transfer rate of 4.0 mb/s and maximum asynchronous data transfer rate of 2.5 mb/s. provides two separate ports for the data bus and the cpu bus. built-in user-programmable timer for selection /reselection time-out operation. supports 8-bit microcomputer bus. support programmed i/o and dma transfer. built-in 48 ma (sinking) scsi port. the scsi port can be used as either single-ended port or differential port. built-in 24-bit data transfer counter. built-in 16-byte fifo. scsi 1 protocol controller cxd1185cq cxd1185cr 64 pin qfp (plastic) 64 pin lqfp (plastic) cxd1185cq/cr
2 cxd1185cq/cr block diagram (cxd1185cq) 2 0 2 9 1 8 1 7 2 2 2 4 2 8 2 3 2 5 4 3 4 4 4 2 5 7 5 9 6 0 1 9 5 5 1 5 + + + + + + 3 0 3 2 3 1 r s t r e s d r q i r q c l k b s y a t n m s g c / d i / o s e l r e q a c k d b p d b 7 - d b 0 d 7 - d 0 5 , 7 - 1 0 , 1 2 - 1 4 4 7 - 5 4 d p s y n c t r a n s f e r c o n t r o l 1 t r a n s f e r b y t e c o u n t e r d m a c o n t r o l f i f o c o u n t e r f i f o i d t i m e - o u t i n t e r r u p t r e q u e s t i n t e r r u p t m a s k c o n f i g u r a t i o n c o m m a n d s t a t u s g e n e r a l - u s e i / o p o r t d e c o d e 3 3 - 4 0 c 7 - c 0 6 1 - 6 4 p 3 - p 0 1 - 4 a 3 - a 0 d a c k i n i t t a r g c s w e r e c o m m a n d i n t e r p r e t e r d i f f e r e n t i a l c o n t r o l s c s i c o n t r o l p a r i t y g e n e r a t e / c h e c k r e s e t c o n t r o l a r b i r a t i o n c o n t r o l s e l e c t i o n c o n t r o l
3 cxd1185cq/cr block diagram (cxd1185cr) 1 8 2 7 1 6 1 5 2 0 2 2 2 6 2 1 2 3 4 1 4 2 4 0 5 5 5 7 5 8 1 7 5 3 1 3 + + + + + + 2 8 3 0 2 9 r s t r e s d r q i r q c l k b s y a t n m s g c / d i / o s e l r e q a c k d b p d b 7 - d b 0 d 7 - d 0 3 , 5 - 8 , 1 0 - 1 2 4 5 - 5 2 d p s y n c t r a n s f e r c o n t r o l 1 d m a c o n t r o l f i f o c o u n t e r f i f o i d i n t e r r u p t r e q u e s t i n t e r r u p t m a s k c o n f i g u r a t i o n c o m m a n d s t a t u s 3 1 - 3 8 c 7 - c 0 5 9 - 6 2 p 3 - p 0 6 3 , 6 4 , 1 , 2 a 3 - a 0 d a c k i n i t t a r g c s w e r e d i f f e r e n t i a l c o n t r o l s c s i c o n t r o l r e s e t c o n t r o l a r b i r a t i o n c o n t r o l s e l e c t i o n c o n t r o l t i m e - o u t t r a n s f e r b y t e c o u n t e r p a r i t y g e n e r a t e / c h e c k d e c o d e g e n e r a l - u s e i / o p o r t c o m m a n d i n t e r p r e t e r
4 cxd1185cq/cr pin configuration c x d 1 1 8 5 c q 5 1 3 3 5 2 6 4 1 1 9 2 0 3 2 c x d 1 1 8 5 c r 4 8 4 9 3 3 3 2 6 4 1 1 6 1 7 pin description pin no. symbol i/o description cxd1185cq cxd1185cr 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 a3 a2 a1 a0 db0 v ss db1 db2 db3 db4 v ss db5 db6 db7 dbp v ss atn bsy ack rst v ss msg sel c/d req v dd v ss i/o i i i i i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o register select signal bit 3 register select signal bit 2 register select signal bit 1 register select signal bit 0 scsi bus db0 signal gnd scsi bus db1 signal scsi bus db2 signal scsi bus db3 signal scsi bus db4 signal gnd scsi bus db5 signal scsi bus db6 signal scsi bus db7 signal scsi bus dbp signal, odd parity gnd scsi bus atn signal scsi bus bsy signal scsi bus ack signal scsi bus rst signal gnd scsi bus msg signal scsi bus sel signal scsi bus c/d signal scsi bus req signal +5 v gnd scsi bus i/o signal
5 cxd1185cq/cr pin no. symbol i/o description cxd1185cq cxd1185cr 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 res cs re we c7 c6 c5 c4 c3 c2 c1 c0 v ss irq drq dack wed red d0 d1 d2 d3 d4 d5 d6 d7 dp v ss clk v dd init targ p0 (doe) p1 (arb) p2 (bsyo) p3 (selo) i i i i i/o i/o i/o i/o i/o i/o i/o i/o o o i i i i/o i/o i/o i/o i/o i/o i/o i/o i/o i o o i/o i/o i/o i/o reset all registers, negative logic chip select signal, negative logic internal register read signal, negative logic internal register write signal, negative logic cpu bus bit 7 cpu bus bit 6 cpu bus bit 5 cpu bus bit 4 cpu bus bit 3 cpu bus bit 2 cpu bus bit 1 cpu bus bit 0 gnd interrupt request signal dma request signal dma acknowledge signal, negative logic data bus write signal, negative logic data bus read signal, negative logic data bus bit 0 data bus bit 1 data bus bit 2 data bus bit 3 data bus bit 4 data bus bit 5 data bus bit 6 data bus bit 7 data bus parity signal gnd clock input, 5 ?6 mhz +5 v initiator operation indicator signal target operation indicator signal general-use port bit 0 (scsi data output authorization) general-use port bit 1 (arbitration in progress) general-use port bit 2 (scsi bsy output) general-use port bit 3 (scsi sel output) all v dd and v ss pins should be connected to the power supply and ground, respectively. items in parentheses ( ) indicate the meaning of the signal when operating in the scsi differential mode. in systems where the cpu and data buses are not separate, connect the wed and red pins to we and re, respectively, and pins d7-d0 to pins c7-c0. if the data bus parity signal is not used, pull up the dp pin using a resistor.
6 cxd1185cq/cr electrical characteristics dc characteristics i/o capacitance ac characteristics (ta=?0 to +75 c, v dd =5 v 10 %) the following capacitances are assumed : input, output pins : 65 pf, input/output pins : 125 pf clock input reset input item supply voltage high level input voltage low level input voltage scsi bus pin input voltage hysteresis high level output voltage low level output voltage scsi bus pin output voltage input leak current input leak current (bidirectional pin) symbol v dd v iht v ilt (v t +)?v t ? v oh v ol v ols i li1 i li2 conditions i oh =? ma i ol =4 ma i ol =48 ma min. typ. max. unit 4.5 5.0 5.5 v 2.2 v 0.8 v 0.2 v v dd ?.5 v 0.4 v 0.5 v ?0 10 a ?0 40 a item input pin output pin input/output pin symbol c in c out c i/o min. typ. max. 9 11 11 unit pf pf pf item clock cycle clock pulse high level width (cycle : 16 mhz) clock pulse low level width (cycle : 16 mhz) symbol tcyc tcknw tcklw min. 5 31 31 typ. max. 16 33 33 unit mhz ns ns item reset pulse width symbol tresw min. 100 typ. max. unit ns c l k t c y c t c k h w t c k l w r e s t r e s w
7 cxd1185cq/cr register write a 3 - a 0 c s w e c 7 - c 0 p 3 - p 0 t a s w t c s s w t w w t c s w t a h w t c s h w t c h w t p d w item address setup time (vs. we ) cs setup time (vs. we ) we pulse width date setup time (vs. we - ) address hold time (vs. we - ) cs hold time (vs. we - ) data hold time (vs. we - ) port delay time (vs. we - ) symbol tasw tcssw tww tcsw tahw tcshw tchw tpdw min. 0 0 70 30 0 0 10 typ. max. 100 unit ns ns ns ns ns ns ns ns register read a 3 - a 0 c s r e c 7 - c 0 p 3 - p 0 t a s r t c s s r t c d r t a h r t c s h r t c h r t p h r t p s r item address setup time (vs. re ) cs setup time (vs. re ) data delay time (vs. re ) address hold time (vs. re - ) cs hold time (vs. re - ) date hold time (vs. re - ) port setup time (vs. re ) port hold time (vs. re - ) symbol tasr tcssr tcdr tahr tcshr tchr tpsr tphr min. 0 0 0 0 5 0 typ. max. 130 25 0 unit ns ns ns ns ns ns ns ns
8 cxd1185cq/cr dma write d r q d a c k w e d d 7 - d 0 , d p t d r l d a t d a s w t w w t d r h d a t d a h w t d a h l t d s w t d h w item drq fall time (vs. dack ) dack setup time (vs. wed ) wed pulse width data setup time (vs. wed - ) dack hold time (vs. wed - ) data hold time (vs. wed - ) drq rise time (vs. dack - ) dack fall time (vs. dack - ) symbol tdrlda tdasw tww tdsw tdahw tdhw tdrhda tdahl min. 0 50 20 10 10 50 typ. max. 70 110 unit ns ns ns ns ns ns ns ns item drq fall time (vs. dack ) dack setup time (vs. red ) data delay time (vs. red ) dack hold time (vs. red - ) data hold time (vs. red - ) drq rise time (vs. dack - ) dack fall time (vs. dack - ) symbol tdrlda tdasr tddr tdahr tdhr tdrhda tdahl min. 0 10 5 50 typ. max. 70 90 25 110 unit ns ns ns ns ns ns ns dma read d r q d a c k r e d d 7 - d 0 , d p t d r l d a t d a s r t d d r t d r h d a t d a h r t d a h l t d h r
9 cxd1185cq/cr initiator asynchronous transfer output a c k r e q d b n t a l r l t d s a t a h r h t d h r item ack fall time (vs. req ) data setup time (vs. ack ) ack rise time (vs. req - ) data hold time (vs. req - ) symbol talrl tdsa tahrh tdhr min. 55 typ. max. 120 90 195 unit ns ns ns ns initiator asynchronous transfer input r e q a c k t a h r h t a l r l item ack fall time (vs. req ) ack rise time (vs. req - ) symbol talrl tahrh min. typ. max. 120 90 unit ns ns target asynchronous transfer input r e q a c k t r l a h t r h a l item req rise time (vs. ack ) req fall time (vs. ack - ) symbol trhal trlah min. typ. max. 90 120 unit ns ns target asynchronous transfer output d b n r e q a c k t d s r t r h a l t d h a t r l a h item data setup time (vs. req ) req rise time (vs. ack ) data hold time (vs. ack ) req fall time (vs. ack - ) symbol tdsr trhal tdha trlah min. 55 typ. max. 90 195 120 unit ns ns ns ns
10 cxd1185cq/cr initiator synchronous transfer output c l k r e q a c k d b n t a l c k h t a h c k h t d h c k h item ack fall time (vs. clk - ) ack rise time ((vs. clk - ) data hold time (vs. clk - ) symbol talckh tahckh tdhckh min. typ. max. 130 100 170 unit ns ns ns symbol trlckh trhckh tdhckh min. typ. max. 130 100 170 unit ns ns ns target synchronous transfer output c l k r e q a c k d b n t r l c k h t r h c k h t d h c k h item req fall time (vs. clk - ) req rise time ((vs. clk - ) data hold time (vs. clk - )
11 cxd1185cq/cr description of functions 1. internal registers the cxd1185c possesses 16 internal registers. the cpu can control the cxd1185c by reading and writing these registers. a summary of the registers is provided below. address 0 1 2 3 4 5 6 7 8 9 a b c d e f read status scsi data interrupt request 1 interrupt request 2 scsi control monitor fifo status scsi id transfer byte counter (low) transfer byte counter (middle) transfer byte counter (high) interrupt authorization 1 interrupt authorization 2 mode sync transfer control scsi bus control i/o port write command ? < * > environment setting selection/reset timer < * > ? ? ? ? ? ? ? ? ? ? < * > no register assigned to this address. 1-1. status register (r0 : r) this register is used to monitor the status of the cxd1185c. 7 6 5 4 3 2 1 0 mrst : monitors the scsi bus rst signal, positive logic. mdbp : monitors the scsi bus dbp signal, positive logic. init : ??when the cxd1185c is in initiator status. when this bit is set to ?? commands which are valid in target status and in initiator status are accepted. targ : ??when the cxd1185c is in target status. when this bit is set to ?? commands which are valid in initiator status and in target status are accepted. trbz : when this bit is set to ?? it indicates that the transfer byte counter count is zero. mirq : monitors the interrupt request signal (irq signal). this bit is set whenever interrupt request occurs and cleared once interrupt request 1 register and interrupt 2 register are read. this bit is not affected by the content of the interrupt authorization register. the logic level of this bit is not affected by the sirm bit in the environment setting register. cip : indicates that a chip command is being executed. while this bit is ?? no new commands can be written to the command register, with the exception of the ?eset chip?command. mrst mdbp init targ trbz mirq cip
12 cxd1185cq/cr 1-2. command register (r0 : w) this is the register to which cxd1185c commands are written. when a command is written to this register, status register bit 0 (cip) is set. when the command is executed and terminated, interrupt request register 2 bit 7 (fnc) is set, and the cip bit and command register are cleared. 7 6 5 4 3 2 1 0 cat1, cat0 : sets the category code given to the cxd1185c. cxd1185c commands are divided into the following four categories : if the current status of the cxd1185c does not match with the category code in the command received, the cip and command registers are cleared. no interrupt is generated in this case. dma : dma mode when this bit is set to ??and a transfer command is executed, dma transfer takes place via the data bus (d7-d0). during the dma transfer, any attempts by the cpu to read/write scsi data register via cpu bus is ignored. trbe : activates the transfer byte counter. when this bit is set to ??and a transfer command is executed, the transfer byte counter is decremented each time a byte of data is transferred. when the counter reaches ??the next data request is stopped. at this point, if the mode where the data is output to scsi or dma mode is ?? the cxd1185c will continue to transfer any data remaining in fifo until it is empty. if a transfer command is executed when this bit is set to ?? 1 byte of data will be transferred regardless of the value of the transfer byte counter and the command will be terminated. in this case the transfer byte counter is not decremented. when dma bit is set, trbe bit must also be set. these two bits can be set simultaneously during command write. cat1 cat0 dma trbe cmd3 cmd2 cmd1 cmd0 cat1 0 0 1 1 cat0 0 1 0 1 mode commands which are valid in any status commands which are valid in disconnected status commands which are valid in target status commands which are valid in initiator status
13 cxd1185cq/cr cmd3, cmd2, cmd1, cmd0 : indicates the command code. the cxd1185c responds to the following commands. see the command description section for detailed information. category 0 0 0 1 1 0 1 1 dma 0 0 0 0 0 0 0 0 0 0 0 0 0 * * * 0 * * * * * 0 0 0 trbe 0 0 0 0 0 0 0 0 0 0 0 0 0 * * * 0 * * * * * 0 0 0 command code 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 command no operation reset chip assert rst flush fifo assert scsi control deassert scsi control assert scsi data deassert scsi data reselect select without atn select with atn enable selection/reselection disable selection/reselection send message send status send data disconnect receive message out receive command receive data transfer information transfer pad deassert ack assert atn deassert atn < * > set ??to activate the mode, set ??to inactivate the mode, except when the dma bit is to ?? trbe bit must also be set to ?? 1-3. scsi data register (r1: r/w) this register is used when transferring data between the scsi bus and the cpu bus. when data is output to the scsi bus via the cpu bus, data can be written to this register if the fifo status register bit 4 (fif) is ?? when data is input from scsi bus, data can be read from this register if the fifo status register bit 7 (fie) is ?? when ?ssert scsi data?is executed, the 16 byte fifo becomes a 1 byte fifo. any value written to the register will be on the scsi bus instantly and a read operation will return the current scsi data bus value. when a dma transfer is performed via the data bus, reads and writes to the scsi data register are performed using the wed, red and dack signals. 1-4. interrupt request registers 1 and 2 these registers show the cause of the interrupt. when an interrupt authorized by interrupt authorization registers 1 or 2 is generated, the irq pin is set immediately. bits in the interrupt request registers 1 and 2 are cleared once the registers are read by the cpu. when all interrupt bits are cleared, mirq bit (in the status register) and the irq pin are cleared. note that interrupt bits in these registers are set regardless of the values in the interrupt authorization registers. if interrupt requests are software polled, interrupt request registers 1 and 2 should only be read when the mirq bit, in the status register, is ??
14 cxd1185cq/cr 1-4-1. interrupt request register 1 (r2 : r) this register? interrupt conditions can be masked in the interrupt authorization register 1. when one of the bits in this register is set, mirq bit in the status register and irq signal are set. if the interrupt bit is authorized in the interrupt authorization register 1, the irq pin is activated simultaneously. 7 6 5 4 3 2 1 0 sto : selection time over indicates a time-out error during selection. also, indicates that the scsi bus rst signal has been driven for the time set in the selection/reset timer if the mode register bit 4 (tmsl) is set to ?? the selection time-out time and scsi bus rst signal drive time are determined by the value of the selection/reset timer register. rsl : reselected indicates that reselection has taken place. fnc bit in the interrupt register 2 is set after reselection. the cpu may not write new commands to the command register until the fnc bit is set. this bit is not set unless the ?nable selection/reselection?command is executed. swa : selection with atn indicates that selection has taken place with the scsi bus atn signal driven. fnc bit in the interrupt register 2 is set after selection. the cpu may not write new commands to the command register until the fnc bit is set. this bit is not set unless the ?nable selection/reselection command is executed. swoa : selection without atn indicates that the selection has taken place. fnc bit in the interrupt register 2 is set after selection. the cpu may not write new commands to the command register until the fnc bit is set. this bit is not set unless the ?nable selection/reselection?command is executed. arbf : arbitration fail indicates that the cxd1185c lost in the arbitration for the right to use the scsi bus. this bit is set when, after receiving a selection/reselection command, the chip waited for bus free and entered arbitration only to be encountered by another device with higher priority. as soon as this bit is set the selection/reselection command is terminated. to participate in another arbitration a new selection/reselection command must be written to the command register. 1-4-2. interrupt request register 2 (r3 : r) this register? interrupt conditions can be masked in the interrupt authorization register 2. when one of the bits in this register is set, mirq bit in the status register and irq signal are set. if the interrupt bit is authorized in the interrupt authorization register 2, the irq pin is activated simultaneously. 7 6 5 4 3 2 1 0 fnc : function complete indicates that the received command was executed and terminated. dcnt : disconnected indicates that a disconnect has taken place in the initiator mode. srst : scsi reset indicates that the scsi bus rst pin was driven. this bit is also set when the ?ssert rst command is executed. sto rsl swa swoa arbf fnc dcnt srst phc datn dpe spe rmsg
15 cxd1185cq/cr phc : phase change indicates that the scsi phase has been changed. this bit is set if the cxd1185c is operating in the initiator mode and the target has changed the scsi phase (msg, i/o, c/d signal), and driven req. datn : drive atn indicates that the scsi bus atn signal has been driven. this bit is set if the cxd1185c is operating in the target mode and the initiator has driven the atn signal. dpe : data bus parity error indicates a parity error on the data bus. this bit is only set if environment setting register bit 5 (dpen) is set to ?? in initial status odd parity (environment register bit 6 set to ?? is selected. spe : scsi bus parity error indicates a parity error on the scsi bus. parity check takes place during the selection phase and data transfer phases. rmsg : req in message phase indicates that the req signal has been driven during the message phase when the cxd1185c is in initiator mode. this bit is used if two different batches of message data have been received during the message phase or if the target requests the message to be resent. 1-5. environment setting register (r3 : w) this register is used to set the operating mode of the cxd1185c. normally, some value must be written to this register immediately after a hardware reset from the cpu. 7 6 5 4 3 2 1 0 dife : selects the differential mode. when this bit is set to ?? general-use i/o port pins p3-p0 are assigned for differential mode bits. sdpm : selects the data bus parity condition. this bit is set to ??for odd parity and to ??for even parity. however, its value is irrelevant if the dpen bit is set to ?? dpen : enables parity generation/check for the data bus. if this bit is set to ?? data bus parity signal is input/output via the dp pin. sirm : select the irq signal logic level. after a hardware reset is performed, the irq signal output is positive logic. to change the irq signal to negative logic. ??must be set in this bit. at this time, the logic level of mirq bit is not affected. fs1, fs0 : used to select the cxd1185c clock division ratio. the appropriate values, as shown in the table below, must be written into these bits to match the external clock frequency applied to the cxd1185c : for the changes made to these bits , ?hip reset?command must be executed. bits fs1 and fs0 are set for a clock division ratio of ??after a hardware reset. dife sdpm dpen sirm fs1 fs0 input frequency (mhz) 16-13 12-9 8-5 fs1 0 0 1 fs0 0 1 * clock division ratio 4 3 2
16 cxd1185cq/cr 1-6. scsi control monitor register (r4 : r) current status of all scsi bus control signals can be read directly from this register. 7 6 5 4 3 2 1 0 mbsy : monitors the scsi bus bsy signal. positive logic. msel : monitors the scsi bus sel signal. positive logic. mmsg : monitors the scsi bus msg signal. positive logic. mcd : monitors the scsi bus c/d signal. positive logic. mio : monitors the scsi bus i/o signal. positive logic. mreq : monitors the scsi bus req signal. positive logic. mack : monitors the scsi bus ack signal. positive logic. matn : monitors the scsi bus atn signal. positive logic. 1-7. selection/reset timer register (r4 : w) this register is used to set the selection time-out time or the scsi bus rst drive time. the real selection time-out time can be calculated by the following equation : time ( s) = div (val+1) 8,192 fcyc fcyc : input frequency (mhz) div : clock division ratio (see section on environment setting register) val : value written to the selection/reset timer register generally the selection time-out time is set to 250 ms. when the selection/reset timer register is used to set the drive time for the rst signal, ??must be written to mode register bit 4 (tmsl). the real rst signal drive time can be calculated by the following equation : time ( s) = div (32 val+38) fcyc fcyc : input frequency (mhz) div : clock division ratio (see section on environment setting register) val : value written to the selection/reset timer register 1-8. fifo status register (r5 : r) this register is for monitoring the fifo status. 7 6 5 4 3 2 1 0 fie : fifo empty indicates that the fifo is empty. fif : fifo full indicates that the fifo is full. fc3, fc2, fc1, fc0 : indicates the number of bytes of data stored in the fifo. mbsy msel mmsg mcd mio mreq mack matn fie fie fc3 fc2 fc1 fc0
17 cxd1185cq/cr 1-9. scsi id register (r6 : r/w) this register is used to set the scsi owner id and the target id for selection. the upper three bits in this register have different meanings each for reads and writes. 7 6 5 4 3 2 1 0 (read) 7 6 5 4 3 2 1 0 (write) sid2, sid1,sid0 : indicates which device last selected/reselected the cxd1185c. smod : when this bit is set to ?? it shows that the chip was selected in single initiator environment. the values in sid2, sid1, sid0 field become invalid. this bit is updated during selection phase. tid2, tid1, tid0 : the target id is written to these bits prior to selection. oid2, oid1, oid0 : the owner id is written to these bits. 1-10. transfer byte counter (high, middle, low) (r9, r8, r7 : r/w) the 24-bit counter calculates the number of transfer bytes during data transfer between scsi bus and the cpu bus or data bus. to activate the transfer byte counter, command register bit 4 (trbe) must be set when writing to the command register. when data is output to the scsi bus, the transfer byte counter is decremented at each rise of the we or wed signal. when data is input from the scsi bus, it is decremented at each fall of the ack signal when in the initiator mode and at each fall of the req signal when in the target mode. 1-11. interrupt authorization registers 1 and 2 (ra, rb : r/w) these registers are used to determine on which interrupt the irq pin should be activated. the bit positions in these two registers correspond to the bit positions in the interrupt request registers. the irq pin will be activated if an interrupt bit becomes ??and the corresponding bit in the interrupt authorization register is also set to ?? see section on interrupt request registers land 2 for the meanings of each bit. 1-12. mode register (rc : r/w) this register is used for setting the modes of the cxd1185c. 7 6 5 4 3 2 1 0 hdpe : when this bit is set to ?? data transfer will be terminated if a parity error is detected on the data bus during a data transfer. however, this bit is irrelevant if environment setting register bit 5 (dpen) is set to ?? hspe : when this bit is set to ?? data transfer will be terminated if a parity error is detected on the scsi bus during a data transfer. hatn : when this bit is ??in target mode, data transfer will be terminated if an atn signal is driven on the scsi bus. tmsl : when this bit is set to ?? the selection/reset timer register is used to set the duration of the scsi bus rst signal. this bit must not be overwritten with a new value if status register bit 0 (cip) is set to ?? if it is required to drive rst signal when the cip bit is ?? first execute ?eset chip command, then overwrite this bit. sid2 sid1 sid0 smod oid2 oid1 oid0 tid2 tid1 tid0 oid2 oid1 oid0 hdpe hspe hatn tmsl sphi sspe bdma
18 cxd1185cq/cr sphi : when this bit is set to ?? if target changes the phase signal during the execution of a transfer command and the req pin is active, interrupt request register 2 bit 4 (phc) is set immediately. if this bit is set to ?? in the mode in which data is input from the scsi bus, the phc bit is not set until all the fifo contents are transferred to the cpu bus or the dma bus. sspe : this bit makes it possible to change the behavior of the chip when there is parity error during selection phase. when this bit is set to ?? the chip will not respond to the selection. when this bit is set to ?? the chip will respond to the selection and causes a scsi parity error interrupt. bdma : burst dma mode. when this bit is set to ?? the drq pin outputs ??for the whole of the dma transfer. 1-13. synchronous transfer control register (rd : r/w) this register is used to set the transfer cycle and the offset for synchronous transfers. 7 6 5 4 3 2 1 0 tpd3, tpd2, tpd1, tpd0 : bits used to set the transfer cycle for synchronous transfers. the transfer cycle is designated according to the following equation : rate ( s) = div (val+2) fcyc 2 fcyc : input frequency (mhz) div : clock division ratio (see section on environment setting register) val : value written to tpd3-0 tof3, tof2, tof1, tof0 : bits used to set the offset for synchronous transfers. the asynchronous transfer mode is selected by writing ??to all of these bits. 1-14. scsi bus control register (re : r/w) this register is used to control the control signals used by the scsi bus. reading this register consists simply of reading the value which was written there previously. however, if the ?ssert scsi control?command is executed, ?? will be read out. the ?ssert scsi control?command must be executed in order to output this register? value to the scsi bus. 7 6 5 4 3 2 1 0 absy : when this bit is set to ?? the scsi bus bsy signal is driven. asel : when this bit is set to ?? the scsi bus sel signal is driven. amsg : when this bit is set to ?? the scsi bus msg signal is driven. however, it is not driven unless the cxd1185c is in the target mode. acd : when this bit is set to ?? the scsi bus c/d signal is driven. however, it is not driven unless the cxd1185c is in the target mode. aio : when this bit is set to ?? the scsi bus i/o signal is driven. however, it is not driven unless the cxd1185c is in the target mode. areq : when this bit is set to ?? the scsi bus req signal is driven. however, it is not driven unless the cxd1185c is in the target mode. aack : when this bit is set to ?? the scsi bus ack signal is driven. however, it is not driven unless the cxd1185c is in the initiator mode. aatn : when this bit is set to ?? the scsi bus atn signal is driven. however, it is not driven unless the cxd1185c is in the initiator mode. tpd3 tpd2 tpd1 tpd0 tof3 tof2 tof1 tof0 absy asel amsg acd aio areq aack aatn
19 cxd1185cq/cr 1-15. i/o port (rf : r/w) this register is used for input/output switching of the general-use 4-bit port and for reading/writing the contents of the port. 7 6 5 4 3 2 1 0 pcn3, pcn2, pcn1, pcn0 : these bits are used for input/output switching of individual bits when pins p3-p0 are used as a general-use port. when a ??is written to any of these bits, the corresponding port is set to the output mode. all these bits are cleared when a hardware reset is performed. note that first ??must be written to all these bits before writing a ??to environment setting register bit 7 (dife). prt3, prt2, prt1, prt0 : this is the 4-bit i/o port. the values written to whichever of these four bits have been set to output mode by pcn3-pcn0 are output via pins p3-p0. by reading these bits it is possible to monitor the values of pins p3-p0 directly. 2. command description this section gives description of all the commands supported by the cxd1185c. with the exception of ?eset chip? the following commands can only be written to the command register when the cip bit in the status register (bit 0) is ?? 2-1. commands valid in any status the following commands can be issued when the cxd1185c is in any of its three statuses : disconnected, initiator or target. no operation this command has no effect on the cxd1185c. however, the fnc bit is set when the command is completed. reset chip this command initializes the cxd1185c. except for the environment setting register, all registers of the cxd1185c are cleared. if the clock division ratio is changed in the environment setting register, this command must be executed. this command can be executed regardless of the value of the cip bit. assert rst this command drives the scsi bus rst pin. when this command is executed, interrupt request register 2 bit 5 (srst) is set and an interrupt is generated. the scsi rst signal is active for 25 s. however, if the rst signal drive duration needs to be changed, it is necessary to set mode register bit 4 (tmsl) to ??and write the drive duration to the selection/reset timer register before executing this command. flush fifo initializes fifo. pcn3 pcn2 pcn1 pcn0 prt3 prt2 prt1 prt0
20 cxd1185cq/cr assert scsi control outputs the value of the scsi bus control register to the scsi bus. in initiator mode ack and atn signals can be asserted. in target mode req, msg, c/d and i/o signals can be asserted. this instruction is only needed in program i/o transfer. on program i/o, see 5-1. deassert scsi control prohibits the content of the scsi bus control register from being output to the scsi bus. once the ?ssert scsi control?command is executed, the scsi bus control signal is output from the scsi bus control register until this command is executed. therefore, the drive of scsi bus control signal must be prohibited depending on needs. assert scsi data outputs the value of the scsi data register to the scsi bus. however, data is not output in the following circumstances : i) a phase change interrupt (phc) is generated in initiator mode. ii) in initiator receive mode (scsi bus i/o signal is high). iii) in target receive mode (scsi bus i/o signal is low). iv) the mode is neither initiator nor target. this instruction is only needed in program i/o transfer. on program i/o, see 5-1. deassert scsi data prohibits the value of the scsi data register from being output to the scsi bus. once the ?ssert scsi data?command is executed, the scsi bus data signals are output from the scsi data register until this command is executed. 2-2. commands valid in disconnected status the following commands are valid only in disconnected status. if any of these commands are issued in any other state, the cip bit and the content of the command register are cleared immediately. reselect this command executes arbitration/reselection from disconnected status. when this command is executed, the cxd1185c switches to the target mode. before issuing this command, the owner id (oid2-0) and target id (tid 2-0) values must be written in the scsi id register. select without atn this command executes arbitration/selection from disconnected status. when this command is executed, the cxd1185c switches to the initiator mode. before issuing this command, the owner id (oid2-0) and target id (tid2-0) values must be written in the scsi id register. select with atn this command executes arbitration/selection from disconnected status. during selection the atn signal is driven on the scsi bus. when this command is executed, the cxd1185c switches to the initiator mode. before issuing this command, the owner id (oid2-0) and target id (tid2-0) values must be set in the scsi id register. if, after this command is executed, message-out phase is to be terminated, the ?eassert atn?command must be executed prior to the transfer of the last message byte.
21 cxd1185cq/cr enable selection/reselection activates selection/reselection interrupts. when this command is executed, the fnc bit is set immediately and the contents of the cip bit and command register are cleared. once this command is executed, rsl/swa/swoa interrupts (in interrupt request 1 register) are set during selection/reselection phase. when one of the selection/reselection is executed this will occur before the fnc interrupt. selection/reselection is automatically disabled for the cases below. hardware reset execution of ?eset chip if one of the above conditions occurs, an ?nable selection/reselection?command must be reloaded in the command register in order to accommodate selection/reselection interrupt. disable selection/reselection prohibits any response to selection/reselection. once this command is executed, the rsl/swoa/swa interrupts in interrupt request register 1 will not be generated. 2-3. commands valid in target status the following commands are valid only in target status. if any of these commands are issued in any other state, the cip bit and the content of the command register are cleared immediately. in the case of data send commands, the transfer data must not be written before the command is written in the command register and the necessary scsi phase change is confirmed by software. in target mode, handshaking on the scsi bus is terminated under the following conditions : 1. the req signal is in any state and if : a hardware reset is performed. the ?eset chip?command is executed. the scsi bus rst pin is driven. 2. the command completes with req inactive if : a parity error is generated on the scsi bus or the data bus. (however, this is not the case if the mode register hdpe and hspe bits are set to ??) the scsi bus atn signal is driven. (however, this is not the case if the mode register hatn bit is set to ??) while the transfer byte counter is in use : the dma bit is set to ?? the status register trbz bit is set to ??and the fifo status register fie bit is set to 1, or in receive mode, the dma bit is set to ??and the status register trbz bit is set to ?? while executing a single byte transfer : the mode is send and the fie bit is set to ?? or the mode is receive and fifo status register bits fc3-fc0 are all set to ?? 3. handshaking is temporarily interrupted with req inactive if : while the transfer byte counter is in use : the mode is send and the fifo status register fie bit is set to ?? or the mode is receive and the fifo status register fif bit is set to ?? during synchronous transfer, the difference in the number of req and ack reaches the offset specified in the synchronous transfer register. the mode is receive, during synchronous transfer, the number of fifo bytes remaining is fewer than the offset specified in the synchronous transfer register.
22 cxd1185cq/cr send message the cxd1185c changes the phase to message in by making the scsi bus msg and i/o signals active and the c/d signal inactive. the message bytes are then sent. if there is more than one message byte or if the message must be sent all at once, the transfer byte counter must be used. send status the cxd1185c changes the phase to status and sends the status byte to the initiator. it makes the scsi bus i/o and c/d signals active and the msg signal inactive. send data the cxd1185c changes the phase to data in and sends the data bytes to the initiator. it makes the scsi bus i/o signal active and msg and c/d signals inactive. if more than one data byte must be sent all at once, the transfer byte counter must be used. disconnect makes all scsi signals inactive, except for the rst signal. receive message out the cxd1185c changes the phase to message in and receives the message bytes from the initiator. it makes the scsi bus msg signal active and the i/o and c/d signals inactive. if there is more than one message byte or if the message must be received all at once, the transfer byte counter must be used. receive command the cxd1185c changes the phase to command and receives the command bytes from the initiator. it makes the scsi bus c/d signal active and msg and i/o signals inactive. if the command bytes must be received all at once, the transfer byte counter must be used. receive data the cxd1185c changes the phase to data out and receives the data bytes from the initiator. it makes the scsi bus msg, c/d and i/o signals inactive and receive the data bytes. if more than one data byte must be received all at once, the transfer byte counter must be used. 2-4. commands valid in initiator status the following commands are valid only in initiator status. if any of these commands are issued in any other state, the cip bit and the content of the command register are cleared immediately. in the case of data send commands, the transfer data must not be written before the command is written in the command register. once the execution of a transfer command is commenced in initiator mode, handshaking on the scsi bus is terminated under the following conditions : 1. the ack signal is in any status and if : a hardware reset is performed. the ?eset chip?command is executed. the scsi bus rst pin is driven.
23 cxd1185cq/cr 2. the command complete with ack inactive if : phase change occurs and phc bit in interrupt request register 2 is set to ?? if this is the case and the dma bit is set to ?? the drq signal also remains inactive. while the transfer byte counter is in use : the dma bit is set to ?? the status register trbz bit is set to ??and the fifo status register fie bit is set to 1, or in receive mode, the dma bit is set to ??and the status register trbz bit is set to ?? while executing a single byte transfer : the mode is send and the fie bit is set to 1, or the mode is receive, fifo status register bits fc3-fc0 are all set to ?? 3. the command complete with ack active if : the mode is receive and a parity error occurs on the scsi bus. (however, this is not the case if the mode register hspe bit is set to ??) status is message-in phase, the trbe bit is set to ?? the req signal is active and a 1-byte message is received. note that in the above two cases the ?eassert ack?command must be executed afterwards. 4. handshaking is temporarily interrupt with ack inactive if : while the transfer byte counter is in use : the mode is send and the fifo status register fie bit is set to ?? during synchronous transfer, the difference in the number of req and ack reaches the offset specified in the synchronous transfer register. the mode is receive, during synchronous transfer, the number of fifo bytes remaining is fewer than the offset specified in the synchronous transfer register. 5. handshaking is temporarily interrupt with ack active if : while the transfer byte counter is in use : the mode is receive and the fifo status register fif bit is set to ?? transfer information in the initiator mode, causes data transfer to take place. transfer pad in the initiator mode, causes data transfer to take place. note that unlike ?ransfer information? the data output by the cxd1185c are all ?? and parity generation is not performed. in addition, no parity check is performed on any data input to the cxd1185c. except for these two exceptions, this command is identical to the ?ransfer information?command. deassert ack makes the scsi ack signal inactive. assert atn makes the scsi atn signal active. deassert atn makes the scsi atn signal inactive. after executing the ?elect with atn?or ?ssert atn?command, the scsi bus atn signal remains active until this command is executed.
24 cxd1185cq/cr 3. reset operation there are four initializing methods for the cxd1185c : hardware reset execution of the ?eset chip?command assertion of rst signal on the scsi bus disconnect 3-1. hardware reset this returns the cxd1185c to its initial status. however, environment setting register bit 1 (fs1) is set to ?? making the initial clock division ratio to ?? all of the internal circuits are also initialized. at this time, the selection/reselection interrupt are disabled. 3-2. execution of the ?eset chip?command the cxd1185c can be initialized by ?eset chip?command (command code ?1?. this command is effective regardless of the cip bit in the status register. this command resets all registers with the exception of the environment setting register. all read only registers except for bits 7 and 6 of the status register and the scsi control monitor register are cleared. since the ?eset chip?command clears all write registers, any scsi bus signal being driven by the cxd1185c will also be cleared. at this time, the selection/reselection interrupt are disabled. 3-3. assertion of rst signal on the scsi bus when the scsi bus rst signal is active, signals on the scsi bus being driven by the cxd1185c are made inactive with the exception of the rst pin. bits 4 and 3 (init and targ bits) are also cleared. 3-4. disconnect if the cxd1185c is operating in initiator mode and a disconnect interrupt is generated, a reset identical to the one in 3-3 takes place. 4. interrupt operation in this section various interrupts, generated by the cxd1185c, are discussed in greater detail. if the internal interrupt conditions of the cxd1185c are satisfied, ?? are written to the appropriate bits in interrupt request registers 1 and 2 and the mirq bit in the status register. irq pin becomes active only if the interrupt is authorized in the interrupt authorization registers. 4-1. arbitration interrupt when a selection command is executed, the cxd1185c waits for bus free. once bus free is detected it outputs the bsy signal and the owner id to the scsi bus and enters arbitration. if, during arbitration, another device with higher priority enters arbitration or if the sel signal is driven on the scsi bus, arbitration fails and arbf is set to ?? the fnc bit is also set a while later. however, if it is not in the bus free state when the selection command is executed, the above operation is performed after bus free is detected. if arbitration is successful it enters selection phase.
25 cxd1185cq/cr 4-2. interrupts when selected/reselected after ?nable selection/reselection?is executed, if the owner id and the sel signal appear on the scsi bus, swoa bit is set to ?? if atn signal also appear at the same time, swa bit is set instead. if i/o signal appears instead of atn signal, then, rsl is set. when any interuppt is generated, the fnc bit is set to ? after a while (6 s max.). the next command cannot be written in the command register till the bit is set. 4-3. interrupts when selection/reselection command is executing when any of ?eselect? ?elect without atn?or ?elect with atn?command is executed, the cxd1185c enters arbitration and after obtaining the right to use the scsi bus it enters selection/reselection phased by sending the target id, the owner id and sel signal onto the bus. at this point, the value of the selection/reset timer register is loaded into the hardware timer (not user accessible) and decrementing begins. note that tmsl bit in the mode register must be ??for the loading to take place. if there is no response from the target device by the time the hardware timer reaches ?? selection time over occurs and the sto bit is set to ??and, afterward, the fnc bit is set to ?? 4-4. data transfer phase interrupts the rmsg and phc bits are valid interrupts only when init bit (status register bit 4) is set to ?? also, the datn bit is valid only when the targ bit (status register bit 3) is set to ?? the spe and dpe bits are valid both in initiator and target modes. the rmsg bit is set to ?? if, in initiator mode, the target device activates req after changing the scsi bus phase to either message-in or message-out. if the message is of multiple byte, it is set each time req in activated. the phc bit is set to ?? if, in initiator mode, the target device activates req after changing the scsi bus phase. if the new phase is either message-in or message-out, rmsg bit is also set to ?? the datn bit is set to ?? if, in target mode, the initiator asserts atn on the scsi bus. once the interrupt request register 2 is read by the cpu, the bit is cleared even if atn continues to be active. the spe bit is set when a parity error is detected on the scsi bus during receive mode data transfer in both initiator and target mode. in initiator mode, it is set on receiving the req. in target mode it is set on receiving the ack. the spe bit is also set if parity error is detected during selection/reselection. dpe bit is set when a parity error is detected on the data bus while writing data into fifo. it is set at the rise of the fifo write signal, wed. this bit is valid only if the dpen bit in the environment setting register is set to ?? if the sdpm bit in the environment register is ?? even parity check is carried out. otherwise odd parity check is carried out. 4-5. other interrupt the srst bit is set to ??when the scsi bus rst signal becomes active. it is also set if the ?ssert rst command is executed and the cxd1185c drives the rst pin. the dcnt bit is set to ??if the cxd1185c is operating in the initiator mode and the target device makes the bsy signal on the scsi bus inactive. normally, in initiator mode, this bit is set at the end of a series of scsi operation when the scsi bus phase becomes bus free. 5. data transfer in this section procedures for transferring data to and from the cxd1185c is described. data can be transferred between the cpu and the cxd1185c in the following three ways : 1. program i/o transfer 2. cpu i/o transfer 3. dma transfer
26 cxd1185cq/cr 5-1. program i/o transfer this method is used to transfer data between the cpu bus and the cxd1185c. the cpu manages scsi handshaking entirely through software. by issuing the ?ssert scsi control?and ?ssert scsi data commands, all of the scsi bus bits can be software controlled. after the above two commands are issued, values can be written to the scsi bus control register and the scsi data register to carry out the scsi handshake. when the ?ssert scsi data?command is issued, the cxd1185c internal fifo counter is fixed at ?? as a result, only one byte of data can be received by the data register. reading the scsi data register results in reading the scsi data bus directly. if the cxd1185c is in neither initiator nor target mode (status register bits 4 and 3 both set to ??, none of the bits in the scsi bus control register can be output to the scsi bus except absy and asel. if the cxd1185c is in initiator mode, the aack and aatn bits are output to the scsi bus. in the target mode, the amsg, acd, aio and areq bits are output. when phase change (phc) interrupt occur in initiator mode, output to the scsi data bus is inhibited. in such case, read the scsi control monitor register and set the phase in the scsi control register. when ?ssert scsi control?command is executed in target mode, pins on the scsi bus, except bsy, are released. the phase can be controlled by setting appropriate values to the scsi bus control register. the contents of the scsi control register and/or scsi data register are output continually after ?ssert scsi control?and/or ?ssert scsi data? therefore, when program i/o transfer is completed the ?eassert scsi control?or ?eassert scsi data?command must be written to the command register. 5-2. cpu i/o transfer this method is used to transfer data between the cpu bus and the cxd1185c without using dma. transfer command can be issued when the cpu is in either the initiator or the target mode. when issuing these commands, command register bit 5 (dma) must be set to ?? outputting data to the scsi bus during the transfer, the cpu must monitor the fifo status and make sure that it does not attempt to write to the fifo when it is full (fifo is full when fif bit in the fifo status register is ?? ( * ). in target mode, after issuing the transfer command, the cpu must check that the scsi bus phase is changed to the appropriate phase, by software, before any transfer data is written. ( * ) before writing a value to the data register a transfer command must be written to the command register. reading data from the scsi bus after a transfer command is written to the command register, the cpu must monitor the fie bit in the fifo status register so as to make sure that it does not attempt to read an empty fifo. the cpu must monitor the fnc bit in the status register to detect the end of transfer. the cpu, at the end of the transfer, must continue to read any remaining data in the fifo. 5-3. dma transfer this method is used to transfer data between the dma bus and the cxd1185c. transfer commands can be issued when the cpu is in either the initiator or the target mode. when issuing commands command register bit 5 (dma) and 4 (trbe) must be set to ?? when a transfer is initiated the drq pin becomes active. then, when the dack pin becomes active, the drq pin becomes inactive (when mode register bit 0 (bdma) is set to ?? and one byte of data is either written to or read from the fifo. if the environment setting register bit 5 (dpen) is set to ?? the data bus parity is calculated from the dp pin. during reads the parity bit is generated, and during writes parity bit check takes place. during dma transfer, the cpu bus and data register are cut off. hence, data register reads/writes from the cpu are ignored.
27 cxd1185cq/cr 6. programming overview the cxd1185c supports scsi phase level commands. as a result, when it is operating it is possible to perform programming without imposing a burden on the software. in this section actual methods for programming the cxd1185c are introduced along with an explanation of all scsi phases, assuming that the cxd1185c is in the initiator mode and the target mode. the below examples show cases where neither reselection phase nor sync transfer is performed. 6-1. initiator mode the cxd1185c is completely initialized when the power is turned on or after a hardware reset. therefore, the following initial settings must be performed. 1 environment setting register initialization the environment setting register is set to an initial value and initial clock division ratio of ?? therefore, a new appropriate value must be written to match the external clock frequency as described in section 1-5. if required, ?? must be written to the other bits at the same time. 2 ?eset chip?command execution the new clock division ratio becomes valid only after executing the ?eset chip?command. (the other bits are valid as soon as they are written.) therefore, if the clock division ratio is to be changed, the ?eset chip?command must be executed after changing the fsi and fso bits in the environment setting register. 3 ?nable selection/reselection?command execution when either a ?ardware reset?or ?eset chip?command is executed, the selection/reselection interrupts are disabled. an ?nable selection/reselection?command must be loaded in the command register in order to accommodate selection/reselection interrupts. 4 scsi id setting the owner id and target id must be written to the scsi id register to prepare for selection. 5 arbitration/selection write ?? to some of the bits of interrupt authorization registers 1 and 2 (arbf, sto, fnc, etc.) as required. write ?elect with atn?command into the command register. if message-out phase is not necessary after selection, instead, write ?elect without atn?command. in this example ?elect with atn?is assumed. wait for the cip bit in the status register to become ??and read the interrupt request registers. if arbitration failed and arbf bit is ?? repeat 4. normally, if selection time over occurs and sto bit set to ?? ?ssert rst?command is executed. 6 switching to the message-out phase wait until the target device switches the scsi bus to the message-out phase (phc bit set to ??. 7 halting atn signal drive execute ?eassert atn?command to inactive the atn signal on the scsi bus. 8 sending message byte confirm that the cip bit is ??in the status register. write ?ransfer information?command to the command register (dma bit and trbe bit are set to ?? for a single byte message). write the message byte into the scsi data register, after confirming that the cip bit is to ?? read interrupt request registers 1 and 2.
28 cxd1185cq/cr 9 switching to the command phase wait until the target device switches the scsi bus to the command phase (phc bit set to ??. 10 command send set the number of command bytes in the transfer byte counter. write ?ransfer information?command into the command register. (this time set the trbe bit to ??and dma bit to ??. write the command bytes into the scsi data register. after confirming that the cip bit is set to ?? read interrupt request registers 1 and 2. 11 switching to the data-in phase wait until the target device switches the scsi bus to the data-in phase (phc bit set to ??. 12 data receive set the number of data bytes received in the transfer byte counter. write ?ransfer information command into the command register (with both dma bit and trbe bit set to ??. note that programming of dma controller is also required starting dma transfer. after confirming that the cip bit is set to ?? read interrupt request registers 1 and 2. 13 switching to the status phase wait until the target devices switches the scsi bus to the status phase (phc bit set to ??. 14 status receive write ?ransfer information?command in the command register (both dma bit and trbe bit are ??. after confirming that the cip bit is set to ?? read interrupt request registers 1 and 2. the status byte is read from the data register. 15 switching to the message-in phase wait until the target device switches the scsi bus to the message-in phase (phc bit set to ??. 16 message receive write ?ransfer information?command in the command register (both dma bit and trbe bit are ??. after confirming that the cip bit is set to ?? read interrupt request registers 1 and 2. the message byte is read from the data register. 17 halting ack signal drive write ?eassert ack?command in the command register to inactivate ack signal. after confirming that the cip bit is ?? read the interrupt request registers 1 and 2. 18 wait until the dcnt bit is set to ?? all scsi phases are covered in 1-17 above. if a disconnect message is sent from the target device when in the data phase, the status phase is skipped and processing continues with the message in phase. when reselection is performed from the target device (rsl bit set to ??, it is necessary to wait until the fnc bit is set to ?? then read the monitor scsi control register and perform the processing appropriate for the current scsi phase.
29 cxd1185cq/cr 6-2. target mode refer to the paragraph for initial settings in initiator mode. 4 scsi id setting write owner id to the scsi id register. 5 arbitration/selection write ?? to at least swa, swoa and fnc bits etc. in the interrupt authorization registers 1 and 2. wait for the initiator to complete arbitration and to begin selection. if selected, either swa or swoa (but, not both) is set in the interrupt request register. if atn was active during selection, swa is set. approximately 10 s later, fnc is set in the interrupt request register 2 and only then d1185a enters target mode. 6 message out phase execution write ?eceive message out?command into the command register (in order to read 1 byte of the message dma and trbe bits should, both, be ??. when bit 0 (cip) of the status register becomes ?? read interrupt request registers 1 and 2. 7 receiving message byte at this point message is already in the data register. read the data register and analyze it. if there is more than 1 byte of message to be received, repeat 5 and 6. 8 ack signal confirmation before the initiator inactivate ack signal on scsi bus, message byte is already fed inside fifo. before executing the next command, it is necessary to confirm that mack bit in the scsi control monitor register is ?? 9 command phase execution write ??to the transfer byte counter, and write ?eceive command?(dma bit is at ??and trbe bit is at ?? command to the command register. read interrupt request registers 1 and 2 when bit 0 (cip) of the status register becomes ?? 10 receive command byte 6 bytes of command data are stored in the data register. read the data register and analyze them. if it is necessary to receive a larger number of command data, repeat 8 and 9. 11 ack signal confirmation it is necessary to confirm that mack bit in the scsi control monitor register is ?? 12 data phase execution set the number of transfer data (in bytes) in the transfer byte counter. write ?end data?(both dma and trbe bits are at ?? command in the command register. when cip bit is ?? read interrupt request registers 1 and 2.
30 cxd1185cq/cr 13 ack signal confirmation it is necessary to confirm that mack bit in the scsi control monitor register is ?? 14 send status byte write ?end status?(both dma and trbe bits are ?? command in the command register. wait until the phase on the scsi bus changes to status phase (monitor scsi control monitor register). write the status byte in the data register. when cip is ?? read interrupt request registers 1 and 2. note: in target mode, when all the following conditions are met, it is necessary to monitor and confirm the change in the scsi bus phase before writing anything in the data register. 1. the command causes a change in the data transfer direction from out to in (e.g. from data out phase to status phase) 2. the command is not executed in dma mode. 15 ack signal confirmation it is necessary to confirm that mack bit in the scsi control monitor register is ?? 16 send message write ?end message?(both dma and trbe bits are ?? command in the command register. if this command causes a change in the data transfer direction from in to out, wait until the phase on the scsi bus changes to message in phase. write the message byte in the data register. when cip is ?? read interrupt request registers 1 and 2. 17 ack signal confirmation it is necessary to confirm that mack bit in the scsi control monitor register is ?? 18 disconnect execution write ?isconnect?command in the command register. when cip is ?? read interrupt request registers 1 and 2. to perform disconnect during data phase, skip status phase and perform message-in phase sequence. to perform reselection, it is necessary to execute ?eselect?command.
31 cxd1185cq/cr appendix a register summary read write 7 6 5 4 3 2 1 0 r0 mrst mdbp init trag trbz mirq cip r1 r2 sto rsl swa swoa arbf r3 fnc dcnt srst phc datn dpe spe rmsg r4 mbsy msel mmsg mcd mio mreq mack matn r5 fie fie fc3 fc2 fc1 fc0 r6 tid2 tid1 tid0 oid2 oid1 oid0 r7 r8 r9 ra sto rsl swa swoa arbf rb fnc dcnt srst phc datn dpe spe rmsg rc hdpe hspe hatn tmsl sphi bdma rd tpd3 tpd2 tpd1 tpd0 tof3 tof2 tof1 tof0 re absy asel amsg acd aio areq aack aatn rf pcn3 pcn2 pcn1 pcn0 prt3 prt2 prt1 prt0 register status register data register interrupt request register 1 interrupt request register 2 scsi control monitor register fifo status register scsi id register transfer byte counter (low) transfer byte counter (middle) transfer byte counter (high) interrupt authorization register 1 interrupt authorization register 2 mode register synchronous transfer register scsi bus control register i/o port register 7 6 5 4 3 2 1 0 r0 cat1 cat0 dma trbe cmd3 dmd2 dmd1 dmd0 r1 r2 r3 dife sdpm dpen sirm fs1 fs0 r4 r5 r6 sid2 sid1 sid0 oid2 oid1 oid0 r7 r8 r9 ra sto rsl swa swoa arbf rb fnc dcnt srst phc datn dpe spe rmsg rc hdpe hspe hatn tmsl sphi bdma rd tpd3 tpd2 tpd1 tpd0 tof3 tof2 tof1 tof0 re absy asel amsg acd aio areq aack aatn rf pcn3 pcn2 pcn1 pcn0 prt3 prt2 prt1 prt0 register command register data register < * > environment setting register selection/reset timer register < * > scsi id register transfer byte counter (low) transfer byte counter (middle) transfer byte counter (high) interrupt authorization register 1 interrupt authorization register 2 mode register synchronous transfer register scsi bus control register i/o port register < * > no register assigned to this address.
32 cxd1185cq/cr appendix b command summary category 0 0 0 1 1 0 1 1 dma 0 0 0 0 0 0 0 0 0 0 0 0 0 * * * 0 * * * * * 0 0 0 trbe 0 0 0 0 0 0 0 0 0 0 0 0 0 * * * 0 * * * * * 0 0 0 command code 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 command no operation reset chip assert rst flush fifo assert scsi control deassert scsi control assert scsi data deassert scsi data reselect select without atn select with atn enable selection/reselection disable selection/reselection send message send status send data disconnect receive message out receive command receive data transfer information transfer pad deassert ack assert atn deassert atn < * > set ??to enable the mode, ??to disable it. however, if the dma bit is set to ?? the trbe bit must also be set to ??
33 cxd1185cq/cr appendix c changes from cxd1185aq the cxd1185cq is pin compatible and comes in the same package as its predecessor, cxd1185aq. the cxd1185c has the identical electrical characteristics as the cxd1185aq. this appendix summarizes the new functions of cxd1185c. new features single initiator mode * detection selection phase scsi parity check/ignore switch single initiator mode detection the cxd1185aq did not support single initiator mode. it was able to be selected under single initiator mode, but since it returned ??for the value of sid2-0, it was impossible to tell whether it was selected by ... a. a scsi device with id ??in multiple initiator environment or b. the sole initiator in single initiator environment. the cxd1185c has a new register bit ?ingle initiator mode?flag to solve the problem. smod single initiator mode flag register scsi id register (06 h) bit bit4 (read only) this flag is updated during every selection phase. note! with this flag, the cxd1185c supports single initiator in target mode. the cxd1185c still does not support execution of single initiator mode selection. therefore, this new feature has no significance to users who wishes to use the cxd1185c as initiator. software changes initiator not required target it is now possible to separate the task after the selection for single initiator environment and multi initiator environment. scsi parity check/ignore switch the cxd1185aq always responded to selection when selection/reselection was enabled. the cxd1185c has an option not to respond to selection when there is scsi parity error. sspe selection scsi parity enable register mode register (0c h) bit bit4 (r/w) * initiators that does not implement the reselection phase and do not operate in multiple initiator environment are allowed to se t only the target? scsi bit during selection phase. smod 0 1 description sid value valid (selected in multi initiator environment) sid value invalid (selected in single initiator environment) sspe 0 1 description respond to selection even when scsi parity error is ignored does not respond to selection when there is scsi parity error
34 cxd1185cq/cr when sppe=? it behaves as a cxd1185aq. it responds to any selection and issues spe (scsi parity error) interrupt (interrupt request register2 (03 h), bit1) when sppe=? does not respond to selection if scsi parity error is detected. software changes if sppe bit is fixed to ?? it behaves as a cxd1185aq, hence no software changes are required. setting sppe bit to ??would eliminate the possibility of spe interrupt after selection and the routine that deals with it. distinguishing cxd1185aq and cxd1185c to distinguish the two by software, follow the steps below. 1. write ??to sppe bit (bit2) of mode register (0c h). 2. read sppe bit (bit2) of mode register (0c h). value of sppe bit 0 1 chip name cxd1185aq cxd1185c
s o n y c o d e e i a j c o d e j e d e c c o d e 2 3 . 9 0 . 4 2 0 . 0 0 . 1 0 . 4 0 . 1 + 0 . 1 5 1 4 . 0 0 . 1 1 1 9 2 0 3 2 3 3 5 1 5 2 6 4 0 . 1 5 0 . 0 5 + 0 . 1 2 . 7 5 0 . 1 5 1 6 . 3 0 . 1 0 . 0 5 + 0 . 2 0 . 8 0 . 2 m 0 . 2 4 0 . 1 5 + 0 . 4 1 7 . 9 0 . 4 + 0 . 4 + 0 . 3 5 6 4 p i n q f p ( p l a s t i c ) q f p - 6 4 p - l 0 1 q f p 0 6 4 - p - 1 4 2 0 p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r / p a l l a d i u m 4 2 / c o p p e r a l l o y p a c k a g e s t r u c t u r e p l a t i n g 1 . 5 g 1 . 0 s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n p l a t i n g 4 2 / c o p p e r a l l o y p a c k a g e s t r u c t u r e 1 2 . 0 0 . 2 * 1 0 . 0 0 . 1 ( 0 . 2 2 ) 0 . 1 8 0 . 0 3 + 0 . 0 8 1 1 6 1 7 3 2 3 3 4 8 4 9 6 4 0 . 1 0 . 1 0 . 5 0 . 2 0 t o 1 0 6 4 p i n l q f p ( p l a s t i c ) l q f p - 6 4 p - l 0 1 l q f p 0 6 4 - p - 1 0 1 0 0 . 3 g d e t a i l a 0 . 5 0 . 2 ( 1 1 . 0 ) 0 . 1 2 7 0 . 0 2 + 0 . 0 5 a 1 . 5 0 . 1 + 0 . 2 0 . 1 s o l d e r / p a l l a d i u m n o t e : d i m e n s i o n * d o e s n o t i n c l u d e m o l d p r o t r u s i o n . 0 . 1 3 m 0 . 5 package outline unit : mm cxd1185cq cxd1185cr cxd1185cq/cr 35

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